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document:1g5-0122 rev.2 page 1 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module description the vp464641641b and vp864641641b are 4mx64-bit and 8mx64-bit small-outline dual-in-line syn- chronous dynamic ram module (sodimm). it is mounted with 4/8 pieces of 4mx16 synchronous dram (vg36641641bt), and each in a standard 54 pin tsop package. decoupling capacitors are mounted on power supply line for noise reduction. the module use serial presence detects implemented via a 2k-bit eeprom component. features vp464641641b, vp864641641b : ? comply to intel pc 100 spuitication ? single 3.3v () power supply ? utilizes -8h, -8l, -10 sdram components ? 32mb (vp464641641b) and 64mb (vp864641641b) ? fully synchronous with all signals referenced to a positive clock edge ? nonbuffered ? programmable burst length (1,2,4,8 & full page) ? programmable wrap sequence (sequential/interleave) ? automatic precharge and controlled precharge ? auto refresh and self refresh modes ? i/o level : lvttl interface ? random column access in every cycle ? 4096 refresh cycles/64ms ? serial presence detect (spd) ? jedec standard pinout ? performance options (at 100mhz) unit: clock marking sdrams cl t rcd t rp t rc -8h -8h 2 2 2 7 -8l -8l 3 2 2 7 -10 -10 3 3 3 8 0.3v
document:1g5-0122 rev.2 page 2 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module pin configuration pin number front side pin name pin number back side pin name pin number front side pin name pin number back side pin name 1 v ss 2 v ss 73 nc 74 ck1 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v dd 46 v dd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 54 dq46 123 dq25 124 dq57 53 dq15 56 dq47 125 dq26 126 dq58 55 v ss 58 v ss 127 dq27 128 dq59 57 nc 60 nc 129 v dd 130 v dd 59 nc 64 nc 131 dq28 132 dq60 61 ck0 66 cke0 133 dq29 134 dq61 63 v dd 68 v dd 135 dq30 136 dq62 65 ras 70 cas 137 dq31 138 dq63 67 we 74 cke1 139 v ss 140 v ss 69 cs0 76 nc 141 sda 142 scl 71 cs1 78 nc 143 v dd 144 v dd 143 front 1 pin assignment (front view) s p d v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t 144 back 2
document:1g5-0122 rev.2 page 3 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module pin description pin name function pin name function a0 ~ a11 address input dqmb0 ~ dqmb7 dq mask enable dq0 ~ dq63 data-in/data - out ck0, ck1 clock input ras row address strobe v dd power cas column address strobe v ss ground we write enable ba0, ba1 bank address scl serial clock cke clock enable sda serial data i/o cs0 , cs1 chip select nc no connect
document:1g5-0122 rev.2 page 4 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module block diagram (4m x 64) cs0 dqmb0 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dqmb4 dq32 dq33 dq34 dq36 dq37 dq38 dq39 dq3 dq35 dqmb1 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dqmb5 dq40 dq41 dq42 dq44 dq45 dq46 dq47 dq11 dq43 dqmb2 dq16 dq17 dq18 dq20 dq21 dq22 dq23 dq19 dqmb3 dq24 dq25 dq26 dq28 dq29 dq30 dq31 dq27 dqmb6 dq48 dq49 dq50 dq52 dq53 dq54 dq55 dq51 dqmb7 dq56 dq57 dq58 dq60 dq61 dq62 dq63 dq59 ras cas we cke0 a0 ~ a11 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 v dd v ss to all sdrams ck1 10 a0 a1 a2 scl serial pd sda w 0.1f m sdram u0 ~ u3 ba0 & ba1 dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u0 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u1 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u2 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u3 cs ck0 sdram u4 ~ u7 sdram u0 ~ u3 10 w
document:1g5-0122 rev.2 page 5 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u0 cs a0 a1 a2 scl serial pd sda ras cas we cke0 a0 ~ a11 sdram u0 ~ u3 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 v dd v ss to all sdrams u0/u1/u2/u3 u4/u5/u6/u7 ck0,1 10 10 block diagram (8m x 64) w w cs1 0.1f m sdram u0 ~ u7 ba0 & ba1 cs0 dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u4 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u2 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u6 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u1 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u5 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u3 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u7 cs dqmb0 dqmb1 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb2 dqmb3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb4 dqmb5 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb6 dqmb7 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 cke1 sdram u4 ~ u7
document:1g5-0122 rev.2 page 6 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module command truth table h : high level, l : low level, v : valid, x : don?t care, n : ck cycle number function symbol cke cs ras cas we ba a10 a0 - a9 a11 n - 1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x mode register set mrs h x l l l l x x v bank activate act h x l l h h v v v read read h x l h l h v l v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x burst stop bst h x l h h l x x x
document:1g5-0122 rev.2 page 7 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module absolute maximum ratings recommended dc operating conditions note 1. overshoot limit: v ih(max.) = v ddq + 2.0v with a pulse width < 3ns 2. undershoot limit: v il =v ssq - 2.0v with a pulse < 3ns and -1.5v with a pulse < 5ns capacitance ta = 25c,f = 1mhz parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0 to +4.6 v supply voltage relative to vss v dd ,v ddq -1.0 to +4.6 v short circuit out put current i out 50 ma power dissipation p d 4mx64 4 w 8mx64 8 operating temperature t opt 0 to +70 c storage temperature t stg -55 to +125 c parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.0 - v dd + 0.3 v 1 input low voltage, all inputs v il -0.3 - 0.8 v 2 parameter symbol size typ max unit input capacitance (address, ras , cas , we ba0, ba1) c11 4m x 64 8m x 64 - 50 85 pf input capacitance (cs0, cs1) c12 4m x 64 8m x 64 - 25 25 pf input capacitance (cke0, cke1) c13 4m x 64 8m x 64 - 50 50 pf input capacitance (ck0~ck1) c14 4m x 64 8m x 64 - 25 25 pf input capacitance(dqmb0 ~ dqmb7) c15 4m x 64 8m x 64 - 15 22 pf data input/output capacitance(dq0 ~ dq63) c16 4m x 64 8m x 64 - 14 20 pf
document:1g5-0122 rev.2 page 8 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dc characteristics (recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vp464641641b -8h -8l -10 unit notes min max min max min max operating current i cc1 burst length = 1 (min .) , io = 0ma one bank active cl = 3 420 420 380 ma 1,2 cl = 2 400 400 350 precharge standby current in power down mode i cc2 p il(max.) t ck = 10ns 12 12 12 ma i cc2 ps il(max) t ck = 8 8 8 precharge standby current in nonpower down mode i cc2 n ih(min.) t ck = 10ns ih(min.) input signals are changed. one time during 30ns. 100 100 100 ma i cc2 ns ih(min.) , t ck = il(max.) input signals are stable. 30 30 30 active standby current in power down mode i cc3 p il(max.) , t ck = 10ns 25 25 25 ma i cc3 ps il(max.) , t ck = 20 20 20 active standby current in nonpower down mode i cc3 n ih(max.) , t ck = 10ns ih(min.) input signals are changed one time during 30ns 100 100 100 ma i cc3 ns ih(min.) t ck = il(max.) input signals are stable. 50 50 50 operating current (burst mode) i cc4 (min.) ,io = 0ma burst length = 4 cl = 3 500 500 400 ma 1,2 cl = 2 330 330 260 refresh current i cc5 (min.) cl = 3 550 550 480 ma 2 cl = 2 525 525 525 self refresh current i cc6 8 8 8 ma input leakage current i li , + 0.3v pins not under test = 0v -40 40 -40 40 -40 40 ua output leakage current i lo , + 0.3v dq# in h - z., dout disabled -5 5 -5 5 -5 5 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v v in 0 3 v in v dd v out 0 3 v out v dd
document:1g5-0122 rev.2 page 9 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dc characteristics (recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vp864641641b -8h -8l 10 unit notes min max min max min max operating current i cc1 burst length = 1 (min .) ,io = 0ma one bank active cl = 3 450 450 420 ma 1,2 cl = 2 430 430 380 precharge standby current in power down mode i cc2 p il(max.) t ck = 15ns 24 24 24 ma i cc2 ps il(max) t ck = 16 16 16 precharge standby current in nonpower down mode i cc2 n ih(min.) t ck = 15ns ih(min.) input signals are changed. one time during 30ns. 200 200 200 ma i cc2 ns ih(min.) , t ck = il(max.) input signals are stable. 60 60 60 active standby current in power down mode i cc3 p il(max.) ,t ck = 15ns 45 45 45 ma i cc3 ps il(max.) ,t ck = 40 40 40 active standby current in nonpower down mode i cc3 n il(max.) ,t ck = 15ns il(min.) input signals are changed one time during 30ns 200 200 200 ma i cc3 ns ih(min.) t ck = il(max.) input signals are stable. 100 100 100 operating current (burst mode) i cc4 (min.) ,io = 0ma burst length=4 cl = 3 510 510 470 ma 1,2 cl = 2 420 350 280 refresh current i cc5 (min.) cl = 3 550 550 520 ma 2 cl = 2 520 520 500 self refresh current i cc6 16 16 16 ma input leakage current i li , + 0.3v pins not under test = 0v -80 80 -80 80 -80 80 ua output leakage current i lo , + 0.3v dq# in h - z., dout disabled -10 10 -10 10 -10 10 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v v in 0 3 v in v dd v out 0 3 v out v dd
document:1g5-0122 rev.2 page 10 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module a.c characteristics test conditions : (ta = 0 to 70c v dd = 3.3v, v ss = 0v) ac input levels(v ih /v il ) 2.0/0.8v input timing reference level/ output timing reference level 1.4v input and fall time 1ns output load condition 50pf parameter cas latency symbol vp464641641b/vp864641641b unit -8h -8l -10 min max min max min max clk cycle time 3 t ck3 8 8 10 ns 2 t ck2 10 12 15 ns clk to valid output delay 3 t ac3 6 6 7 ns 2 t ac2 6 8 8 ns clk high pulse width t ch 3 3 3 ns clk low pulse width t cl 3 3 3 ns cke setup time t cks 2 2 2 ns cke hold time t ckh 1 1 1 ns address setup time t as 2 2 2 ns address hold time t ah 1 1 1 ns command setup time t cms 2 2 2 ns command hold time t cmh 1 1 1 ns data - in setup time t ds 2 2 2 ns data - in hold time t dh 1 1 1 ns output data hold time t oh 3 3 3 ns clk to output on low - z t lz 0 0 0 ns clk to output in hi - z 3 t hz 6 6 7 ns 2 6 8 8 clk to output in hi - z without load t ohn 1 2 2 ns row active to active delay t rrd 16 20 24 ns ras to cas delay t rcd 20 20 20 ns row precharge time t rp 20 24 30 ns row active time t ras 46 120k 46 120k 50 120k ns row cycle time t rc 70 70 80 ns last data in to burst stop t bdl 1clk 1clk 1clk ns data - in to act (ref) command (auto precharge) t dal 1clk + t rp 1clk + t rp 1clk + t rp ns data - in to precharge t dpl 1 clk 1 clk 1 clk ns transition time t t 1 10 1 10 1 10 ns mode reg. set cycle t rsc 2 clk 2 clk 2 clk ns power down exit setup time t pde 2 3 3 ns self refresh exit time t srx 1 1 1 ns refresh time t ref 64 64 64 ms 0.3v
document:1g5-0122 rev.2 page 11 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module serial presence detect information 32 mb byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128 bytes 80 1 total spd memory size 256 bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 8 08 5 number of banks on module 1 row 01 6 module data width 64 bits 40 7 module data width (continued) 0 00 8 module voltage interface levels lvttl 01 9 sdram cycle time. cas latency = 3 8ns 8ns 10ns 80 80 a0 10 sdram access from clock. cas latency = 3 6ns 6ns 7ns 60 60 70 11 module configuration type non-parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x16 10 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8,page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes : general 0e 0e 23 sdram cycle time. cas latency = 2 10ns 12ns 15ns a0 18 1e 24 sdram access from clock. cas latency = 2 6ns 8ns 8ns 60 14 18 27 min. row precharge time 20ns 24ns 30ns 14 14 14 28 min. row active to row active 16ns 20ns 24ns 10 2e 32 29 min. ras to cas delay 20ns 20ns 20ns 14 08 08 30 min. ras pulse width 46ns 46ns 50ns 2e 12 12 31 module bank density 32mb 08 62 spd data revision code rev.1, 2 12 63 checksum for bytes 0-62 checksum data 7c 9e dc 64 manufacturer ? s jedec id code continuation code 7f 65 manufacturer ? s jedec id code vanguard 29 66-71 manufacturer ? s jedec id code none ff
document:1g5-0122 rev.2 page 12 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module byte function described function supported hex -8h -8l 10 -8h -8l 10 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number p 50 75 manufacture?s part number 4 34 76 manufacture?s part number 6 36 77 manufacture?s part number 4 34 78 manufacture?s part number 6 36 79 manufacture?s part number 4 34 80 manufacture?s part number 1 31 81 manufacture?s part number 6 36 82 manufacture?s part number 4 34 83 manufacture?s part number 1 31 84 manufacture?s part number b 42 85 manufacture?s part number t 54 86 manufacture?s part number g(gold lead) s(tin lead) 47 53 87 manufacture?s part number a 41 88 manufacture?s part number ?-? 2d 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturing data year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information af ad ad 128~255 for customer usc none ff
document:1g5-0122 rev.2 page 13 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module serial presence detect information 64 mb byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128 bytes 80 1 total spd memory size 256 bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 8 08 5 number of banks on module 2 row 02 6 module data width 64 bits 40 7 module data width (continued) 0 00 8 module voltage interface levels lvttl 01 9 sdram cycle time. cas latency = 3 8ns 8ns 10ns 80 80 a0 10 sdram access from clock. cas latency = 3 6ns 6ns 7ns 60 60 70 11 module configuration type non-parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x16 10 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8,page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes : general 0e 0e 23 sdram cycle time. cas latency = 2 10ns 12ns 15ns a0 18 1e 24 sdram access from clock. cas latency = 2 6ns 8ns 8ns 60 14 18 27 min. row precharge time 20ns 24ns 30ns 14 14 14 28 min. row active to row active 16ns 20ns 24ns 10 2e 32 29 min. ras to cas delay 20ns 20ns 20ns 14 08 08 30 min. ras pulse width 46ns 46ns 50ns 2e 12 12 31 module bank density 32mb 08 62 spd data revision code rev.1, 2 12 63 checksum for bytes 0-62 checksum data 7d 9f dd 64 manufacturer ?s jedec id code continuation code 7f 65 manufacturer ? s jedec id code vanguard 29 66-71 manufacturer ? s jedec id code none ff
document:1g5-0122 rev.2 page 14 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module byte function described function supported hex -8h -8l 10 -8h -8l 10 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number p 50 75 manufacture?s part number 8 38 76 manufacture?s part number 6 36 77 manufacture?s part number 4 34 78 manufacture?s part number 6 36 79 manufacture?s part number 4 34 80 manufacture?s part number 1 31 81 manufacture?s part number 6 36 82 manufacture?s part number 4 34 83 manufacture?s part number 1 31 84 manufacture?s part number b 42 85 manufacture?s part number t 54 86 manufacture?s part number g(gold lead) s(tin lead) 47 53 87 manufacture?s part number a 41 88 manufacture?s part number ?-? 2d 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturing data year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information ff fd fd 128~255 for customer usc none ff
document:1g5-0122 rev.2 page 15 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module 144 pin sodimm mechanical dimension(front side) note : the use device is tsop sdram all dimensions are typical unless otherwise stated. (millimeters) detail b detail a 8mx64 side 4mx64 side b a o 1.8x2 front
document:1g5-0122 rev.2 page 16 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module ordering information 1 2 3 4 5 6 7 8 9 10 v x xx xx xxxxxx x x x x x -x v : vis product 1 : ram family p: sdram sodimm(144pin) 2 : memory density (work) 4 : 4m 8 : 8m 3 : i/o width 64 : x 64 4 : operation mode and refresh with different density 641641 : 4k ref., 4m x16 sdram 5 : component revision blank : none a : a revision b : b revision c : c revision 6 : component package t : tsop 7 : pc board finger plating g : gold s : tin/lead 8 : pc board revision blank : none a : a revision b : b revision c : c revision 9 : customer specific blank : none 10 : module speed -8h : 100mhz, cl = 2, t rp = 2, t rcd = 2 -8l : 100mhz, cl = 3, t rp = 2, t rcd = 2 -10 : 100mhz, cl = 3, t rp = 3, t rcd = 3
document:1g5-0122 rev.2 page 1 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module description the vp464641641b and vp864641641b are 4mx64-bit and 8mx64-bit small-outline dual-in-line syn- chronous dynamic ram module (sodimm). it is mounted with 4/8 pieces of 4mx16 synchronous dram (vg36641641bt), and each in a standard 54 pin tsop package. decoupling capacitors are mounted on power supply line for noise reduction. the module use serial presence detects implemented via a 2k-bit eeprom component. features vp464641641b, vp864641641b : ? comply to intel pc 100 spuitication ? single 3.3v () power supply ? utilizes -8h, -8l, -10 sdram components ? 32mb (vp464641641b) and 64mb (vp864641641b) ? fully synchronous with all signals referenced to a positive clock edge ? nonbuffered ? programmable burst length (1,2,4,8 & full page) ? programmable wrap sequence (sequential/interleave) ? automatic precharge and controlled precharge ? auto refresh and self refresh modes ? i/o level : lvttl interface ? random column access in every cycle ? 4096 refresh cycles/64ms ? serial presence detect (spd) ? jedec standard pinout ? performance options (at 100mhz) unit: clock marking sdrams cl t rcd t rp t rc -8h -8h 2 2 2 7 -8l -8l 3 2 2 7 -10 -10 3 3 3 8 0.3v
document:1g5-0122 rev.2 page 2 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module pin configuration pin number front side pin name pin number back side pin name pin number front side pin name pin number back side pin name 1 v ss 2 v ss 73 nc 74 ck1 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v dd 46 v dd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 54 dq46 123 dq25 124 dq57 53 dq15 56 dq47 125 dq26 126 dq58 55 v ss 58 v ss 127 dq27 128 dq59 57 nc 60 nc 129 v dd 130 v dd 59 nc 64 nc 131 dq28 132 dq60 61 ck0 66 cke0 133 dq29 134 dq61 63 v dd 68 v dd 135 dq30 136 dq62 65 ras 70 cas 137 dq31 138 dq63 67 we 74 cke1 139 v ss 140 v ss 69 cs0 76 nc 141 sda 142 scl 71 cs1 78 nc 143 v dd 144 v dd 143 front 1 pin assignment (front view) s p d v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t v g 3 6 6 4 1 6 4 1 b t 144 back 2
document:1g5-0122 rev.2 page 3 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module pin description pin name function pin name function a0 ~ a11 address input dqmb0 ~ dqmb7 dq mask enable dq0 ~ dq63 data-in/data - out ck0, ck1 clock input ras row address strobe v dd power cas column address strobe v ss ground we write enable ba0, ba1 bank address scl serial clock cke clock enable sda serial data i/o cs0 , cs1 chip select nc no connect
document:1g5-0122 rev.2 page 4 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module block diagram (4m x 64) cs0 dqmb0 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dqmb4 dq32 dq33 dq34 dq36 dq37 dq38 dq39 dq3 dq35 dqmb1 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dqmb5 dq40 dq41 dq42 dq44 dq45 dq46 dq47 dq11 dq43 dqmb2 dq16 dq17 dq18 dq20 dq21 dq22 dq23 dq19 dqmb3 dq24 dq25 dq26 dq28 dq29 dq30 dq31 dq27 dqmb6 dq48 dq49 dq50 dq52 dq53 dq54 dq55 dq51 dqmb7 dq56 dq57 dq58 dq60 dq61 dq62 dq63 dq59 ras cas we cke0 a0 ~ a11 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 sdram u0 ~ u3 v dd v ss to all sdrams ck1 10 a0 a1 a2 scl serial pd sda w 0.1f m sdram u0 ~ u3 ba0 & ba1 dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u0 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u1 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u2 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u3 cs ck0 sdram u4 ~ u7 sdram u0 ~ u3 10 w
document:1g5-0122 rev.2 page 5 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u0 cs a0 a1 a2 scl serial pd sda ras cas we cke0 a0 ~ a11 sdram u0 ~ u3 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 v dd v ss to all sdrams u0/u1/u2/u3 u4/u5/u6/u7 ck0,1 10 10 block diagram (8m x 64) w w cs1 0.1f m sdram u0 ~ u7 ba0 & ba1 cs0 dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u4 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u2 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u6 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u1 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u5 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u3 cs dqml dqmu dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 u7 cs dqmb0 dqmb1 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb2 dqmb3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb4 dqmb5 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 dqmb6 dqmb7 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dq11 cke1 sdram u4 ~ u7
document:1g5-0122 rev.2 page 6 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module command truth table h : high level, l : low level, v : valid, x : don?t care, n : ck cycle number function symbol cke cs ras cas we ba a10 a0 - a9 a11 n - 1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x mode register set mrs h x l l l l x x v bank activate act h x l l h h v v v read read h x l h l h v l v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x burst stop bst h x l h h l x x x
document:1g5-0122 rev.2 page 7 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module absolute maximum ratings recommended dc operating conditions note 1. overshoot limit: v ih(max.) = v ddq + 2.0v with a pulse width < 3ns 2. undershoot limit: v il =v ssq - 2.0v with a pulse < 3ns and -1.5v with a pulse < 5ns capacitance ta = 25c,f = 1mhz parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0 to +4.6 v supply voltage relative to vss v dd ,v ddq -1.0 to +4.6 v short circuit out put current i out 50 ma power dissipation p d 4mx64 4 w 8mx64 8 operating temperature t opt 0 to +70 c storage temperature t stg -55 to +125 c parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.0 - v dd + 0.3 v 1 input low voltage, all inputs v il -0.3 - 0.8 v 2 parameter symbol size typ max unit input capacitance (address, ras , cas , we ba0, ba1) c11 4m x 64 8m x 64 - 50 85 pf input capacitance (cs0, cs1) c12 4m x 64 8m x 64 - 25 25 pf input capacitance (cke0, cke1) c13 4m x 64 8m x 64 - 50 50 pf input capacitance (ck0~ck1) c14 4m x 64 8m x 64 - 25 25 pf input capacitance(dqmb0 ~ dqmb7) c15 4m x 64 8m x 64 - 15 22 pf data input/output capacitance(dq0 ~ dq63) c16 4m x 64 8m x 64 - 14 20 pf
document:1g5-0122 rev.2 page 8 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dc characteristics (recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vp464641641b -8h -8l -10 unit notes min max min max min max operating current i cc1 burst length = 1 (min .) , io = 0ma one bank active cl = 3 420 420 380 ma 1,2 cl = 2 400 400 350 precharge standby current in power down mode i cc2 p il(max.) t ck = 10ns 12 12 12 ma i cc2 ps il(max) t ck = 8 8 8 precharge standby current in nonpower down mode i cc2 n ih(min.) t ck = 10ns ih(min.) input signals are changed. one time during 30ns. 100 100 100 ma i cc2 ns ih(min.) , t ck = il(max.) input signals are stable. 30 30 30 active standby current in power down mode i cc3 p il(max.) , t ck = 10ns 25 25 25 ma i cc3 ps il(max.) , t ck = 20 20 20 active standby current in nonpower down mode i cc3 n ih(max.) , t ck = 10ns ih(min.) input signals are changed one time during 30ns 100 100 100 ma i cc3 ns ih(min.) t ck = il(max.) input signals are stable. 50 50 50 operating current (burst mode) i cc4 (min.) ,io = 0ma burst length = 4 cl = 3 500 500 400 ma 1,2 cl = 2 330 330 260 refresh current i cc5 (min.) cl = 3 550 550 480 ma 2 cl = 2 525 525 525 self refresh current i cc6 8 8 8 ma input leakage current i li , + 0.3v pins not under test = 0v -40 40 -40 40 -40 40 ua output leakage current i lo , + 0.3v dq# in h - z., dout disabled -5 5 -5 5 -5 5 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v v in 0 3 v in v dd v out 0 3 v out v dd
document:1g5-0122 rev.2 page 9 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module dc characteristics (recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vp864641641b -8h -8l 10 unit notes min max min max min max operating current i cc1 burst length = 1 (min .) ,io = 0ma one bank active cl = 3 450 450 420 ma 1,2 cl = 2 430 430 380 precharge standby current in power down mode i cc2 p il(max.) t ck = 15ns 24 24 24 ma i cc2 ps il(max) t ck = 16 16 16 precharge standby current in nonpower down mode i cc2 n ih(min.) t ck = 15ns ih(min.) input signals are changed. one time during 30ns. 200 200 200 ma i cc2 ns ih(min.) , t ck = il(max.) input signals are stable. 60 60 60 active standby current in power down mode i cc3 p il(max.) ,t ck = 15ns 45 45 45 ma i cc3 ps il(max.) ,t ck = 40 40 40 active standby current in nonpower down mode i cc3 n il(max.) ,t ck = 15ns il(min.) input signals are changed one time during 30ns 200 200 200 ma i cc3 ns ih(min.) t ck = il(max.) input signals are stable. 100 100 100 operating current (burst mode) i cc4 (min.) ,io = 0ma burst length=4 cl = 3 510 510 470 ma 1,2 cl = 2 420 350 280 refresh current i cc5 (min.) cl = 3 550 550 520 ma 2 cl = 2 520 520 500 self refresh current i cc6 16 16 16 ma input leakage current i li , + 0.3v pins not under test = 0v -80 80 -80 80 -80 80 ua output leakage current i lo , + 0.3v dq# in h - z., dout disabled -10 10 -10 10 -10 10 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v v in 0 3 v in v dd v out 0 3 v out v dd
document:1g5-0122 rev.2 page 10 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module a.c characteristics test conditions : (ta = 0 to 70c v dd = 3.3v, v ss = 0v) ac input levels(v ih /v il ) 2.0/0.8v input timing reference level/ output timing reference level 1.4v input and fall time 1ns output load condition 50pf parameter cas latency symbol vp464641641b/vp864641641b unit -8h -8l -10 min max min max min max clk cycle time 3 t ck3 8 8 10 ns 2 t ck2 10 12 15 ns clk to valid output delay 3 t ac3 6 6 7 ns 2 t ac2 6 8 8 ns clk high pulse width t ch 3 3 3 ns clk low pulse width t cl 3 3 3 ns cke setup time t cks 2 2 2 ns cke hold time t ckh 1 1 1 ns address setup time t as 2 2 2 ns address hold time t ah 1 1 1 ns command setup time t cms 2 2 2 ns command hold time t cmh 1 1 1 ns data - in setup time t ds 2 2 2 ns data - in hold time t dh 1 1 1 ns output data hold time t oh 3 3 3 ns clk to output on low - z t lz 0 0 0 ns clk to output in hi - z 3 t hz 6 6 7 ns 2 6 8 8 clk to output in hi - z without load t ohn 1 2 2 ns row active to active delay t rrd 16 20 24 ns ras to cas delay t rcd 20 20 20 ns row precharge time t rp 20 24 30 ns row active time t ras 46 120k 46 120k 50 120k ns row cycle time t rc 70 70 80 ns last data in to burst stop t bdl 1clk 1clk 1clk ns data - in to act (ref) command (auto precharge) t dal 1clk + t rp 1clk + t rp 1clk + t rp ns data - in to precharge t dpl 1 clk 1 clk 1 clk ns transition time t t 1 10 1 10 1 10 ns mode reg. set cycle t rsc 2 clk 2 clk 2 clk ns power down exit setup time t pde 2 3 3 ns self refresh exit time t srx 1 1 1 ns refresh time t ref 64 64 64 ms 0.3v
document:1g5-0122 rev.2 page 11 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module serial presence detect information 32 mb byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128 bytes 80 1 total spd memory size 256 bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 8 08 5 number of banks on module 1 row 01 6 module data width 64 bits 40 7 module data width (continued) 0 00 8 module voltage interface levels lvttl 01 9 sdram cycle time. cas latency = 3 8ns 8ns 10ns 80 80 a0 10 sdram access from clock. cas latency = 3 6ns 6ns 7ns 60 60 70 11 module configuration type non-parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x16 10 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8,page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes : general 0e 0e 23 sdram cycle time. cas latency = 2 10ns 12ns 15ns a0 18 1e 24 sdram access from clock. cas latency = 2 6ns 8ns 8ns 60 14 18 27 min. row precharge time 20ns 24ns 30ns 14 14 14 28 min. row active to row active 16ns 20ns 24ns 10 2e 32 29 min. ras to cas delay 20ns 20ns 20ns 14 08 08 30 min. ras pulse width 46ns 46ns 50ns 2e 12 12 31 module bank density 32mb 08 62 spd data revision code rev.1, 2 12 63 checksum for bytes 0-62 checksum data 7c 9e dc 64 manufacturer ? s jedec id code continuation code 7f 65 manufacturer ? s jedec id code vanguard 29 66-71 manufacturer ? s jedec id code none ff
document:1g5-0122 rev.2 page 12 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module byte function described function supported hex -8h -8l 10 -8h -8l 10 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number p 50 75 manufacture?s part number 4 34 76 manufacture?s part number 6 36 77 manufacture?s part number 4 34 78 manufacture?s part number 6 36 79 manufacture?s part number 4 34 80 manufacture?s part number 1 31 81 manufacture?s part number 6 36 82 manufacture?s part number 4 34 83 manufacture?s part number 1 31 84 manufacture?s part number b 42 85 manufacture?s part number t 54 86 manufacture?s part number g(gold lead) s(tin lead) 47 53 87 manufacture?s part number a 41 88 manufacture?s part number ?-? 2d 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturing data year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information af ad ad 128~255 for customer usc none ff
document:1g5-0122 rev.2 page 13 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module serial presence detect information 64 mb byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128 bytes 80 1 total spd memory size 256 bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 8 08 5 number of banks on module 2 row 02 6 module data width 64 bits 40 7 module data width (continued) 0 00 8 module voltage interface levels lvttl 01 9 sdram cycle time. cas latency = 3 8ns 8ns 10ns 80 80 a0 10 sdram access from clock. cas latency = 3 6ns 6ns 7ns 60 60 70 11 module configuration type non-parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x16 10 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8,page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes : general 0e 0e 23 sdram cycle time. cas latency = 2 10ns 12ns 15ns a0 18 1e 24 sdram access from clock. cas latency = 2 6ns 8ns 8ns 60 14 18 27 min. row precharge time 20ns 24ns 30ns 14 14 14 28 min. row active to row active 16ns 20ns 24ns 10 2e 32 29 min. ras to cas delay 20ns 20ns 20ns 14 08 08 30 min. ras pulse width 46ns 46ns 50ns 2e 12 12 31 module bank density 32mb 08 62 spd data revision code rev.1, 2 12 63 checksum for bytes 0-62 checksum data 7d 9f dd 64 manufacturer ?s jedec id code continuation code 7f 65 manufacturer ? s jedec id code vanguard 29 66-71 manufacturer ? s jedec id code none ff
document:1g5-0122 rev.2 page 14 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module byte function described function supported hex -8h -8l 10 -8h -8l 10 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number p 50 75 manufacture?s part number 8 38 76 manufacture?s part number 6 36 77 manufacture?s part number 4 34 78 manufacture?s part number 6 36 79 manufacture?s part number 4 34 80 manufacture?s part number 1 31 81 manufacture?s part number 6 36 82 manufacture?s part number 4 34 83 manufacture?s part number 1 31 84 manufacture?s part number b 42 85 manufacture?s part number t 54 86 manufacture?s part number g(gold lead) s(tin lead) 47 53 87 manufacture?s part number a 41 88 manufacture?s part number ?-? 2d 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturing data year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information ff fd fd 128~255 for customer usc none ff
document:1g5-0122 rev.2 page 15 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module 144 pin sodimm mechanical dimension(front side) note : the use device is tsop sdram all dimensions are typical unless otherwise stated. (millimeters) detail b detail a 8mx64 side 4mx64 side b a o 1.8x2 front
document:1g5-0122 rev.2 page 16 vis vp464641641b,vp864641641b preliminary 4m, 8mx64-bit sdram sod imm module ordering information 1 2 3 4 5 6 7 8 9 10 v x xx xx xxxxxx x x x x x -x v : vis product 1 : ram family p: sdram sodimm(144pin) 2 : memory density (work) 4 : 4m 8 : 8m 3 : i/o width 64 : x 64 4 : operation mode and refresh with different density 641641 : 4k ref., 4m x16 sdram 5 : component revision blank : none a : a revision b : b revision c : c revision 6 : component package t : tsop 7 : pc board finger plating g : gold s : tin/lead 8 : pc board revision blank : none a : a revision b : b revision c : c revision 9 : customer specific blank : none 10 : module speed -8h : 100mhz, cl = 2, t rp = 2, t rcd = 2 -8l : 100mhz, cl = 3, t rp = 2, t rcd = 2 -10 : 100mhz, cl = 3, t rp = 3, t rcd = 3

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